The present invention relates to a semiconductor memory and a process for fabricating the same, and more specifically, to a semiconductor memory in which a memory cell is formed on a semiconductor substrate to be constituted of a memory cell selecting transistor and a capacitor having a capacitor dielectric film formed of a ferroelectric material or a highly dielectric material in order to store information, and a process for fabricating the same.
Recently, a technology of a semiconductor memory having a capacitor dielectric film formed of a ferroelectric material or a highly dielectric material is actively developed. This semiconductor memory is so configured to store the information by utilizing polarization of the ferroelectric or highly dielectric material capacitor or whether or not an electric charge is stored in the highly dielectric material capacitor.
Referring to FIG. 7, there is shown a diagrammatic sectional view of a prior art memory cell. As shown in FIG. 7, source/drain diffused layers 102 are formed on a surface region of a semiconductor substrate (silicon substrate ) 101, and a gate electrode 103 is formed on a gate insulating film (not shown) formed on the semiconductor substrate 101. Thus, a field effect transistor constituting a memory cell selecting transistor is formed. A bit line is constituted of a first metal interconnection 105, which is electrically connected through a first plug (contact plug) 104 to one of the diffused layers 102 of the field effect transistor.
Above the field effect transistor, an interlayer insulator film, the first metal interconnection 105 and the first plug 104, are formed, and thereon, a capacitor is formed, which is constituted of a barrier layer 107, a lower electrode 111 and a ferroelectric material film (or highly dielectric material film) 112 and an upper electrode 113. The lower electrode 111 is electrically connected to the other of the diffused layers 102, through the barrier layer 107, the second plug (via plug) 106, the first metal interconnection 105 and the first plug 104. With this arrangement, a word line functions as the gate electrode 103 of the field electric transistor.
Incidentally, in FIG. 7, the interlayer insulator film 118 is formed of a first interlayer insulator film which is firmed on the semiconductor substrate and on which the first metal interconnection 105 is formed, and a second interlayer insulator film which is formed on the first interlayer insulator film and on which the barrier layer 107 is formed. However, the first and second interlayer insulator films are shown as a single interlayer insulator film 118.
The ferroelectric material film (high dielectric material film) 112 is formed of for example PZT (PbZrxTi1xe2x88x92xO3) or SBT (SrBi2Ta2O9), and formed by CVD (chemical vapor deposition) or another, as disclosed in for example JP-A-11-317500.
A capacitor cover insulating film 115 is formed on the capacitor, and a second metal interconnection 116 is formed as a plate line on the cover film 115.
In many cases, it is required to form the ferroelectric (high dielectric) material film in an oxidizing atmosphere or to anneal the ferroelectric (high dielectric) material film in an oxygen atmosphere after the ferroelectric (high dielectric) material film is formed, in order to stabilize the ferroelectric (high dielectric) material film. Because of this, the lower electrode 111 and the upper electrode 113 are formed of a platinum metal such as Pt, Ir and Ru, or alternatively a conductive oxide of platinum metal such as IrO2, RuO2, and SrRuO2. As shown in for example JP-A-08-236719, the barrier film 107 is provided to prevent the material of the plug from diffusing upward, and is formed of TiN in ordinary cases.
The first and second interconnections 105 and 116 are required to have an easy fine patterning, an excellent tight adhesion to SiO2 which forms the interlayer insulator film 118 and the capacitor cover film 115, and a low electric resistivity, and are formed of a multilayer film using WSi2, Ti, TiN or Al, for example.
On the second metal interconnection 116, a passivation film 117 is formed by forming a film of silicon nitride (SiNx) or silicon oxynitride film (SiOxNy) in a plasma CVD process. Incidentally, as described in JP-A-07-245237, it is known that a data rewriting anti-fatigue property in a semiconductor memory is greatly dependent upon the material which constitutes the lower electrode 111 in contact with the ferroelectric (or high dielectric) material film. If the lower electrode 111 is formed of Ir, Ru or a conductive oxide such as IrO2, RuO2, and SrRuO2, the data rewriting anti-fatigue property can be remarkably improved. Because of this, these materials are used to form the lower electrode 111.
In the case that the lower electrode 111 is formed of Ir, Ru or a conductive oxide such as IrO2, RuO2, and SrRuO2, it is known as shown in JP-A-06-326249 that in consideration of the tight adhesion with the lower electrode and the semiconductor substrate, the barrier layer is formed of TiN/Ti (lower layer of Ti and upper layer of TiN), and a ferroelectric (high dielectric) material film is deposited on a multilayer film which is formed by forming the barrier layer and the lower electrode in the named order.
However, the inventors have discovered a problem that when the multilayer film is formed by forming the barrier layer (formed of TiN/Ti) and the lower electrode in the named order on the semiconductor substrate having a plug formed therein (in which the plug is exposed at a surface of the interlayer insulator film), and then, the ferroelectric (high dielectric) material film is deposited on the multilayer film, the lower electrode is pealed off and is lifted up from the barrier layer (TiN/Ti), only in a region positioned above the plug.
Referring to FIG. 8A, there is shown a scanning electron microscope photograph of a section of one example, in which on a semiconductor substrate having a W plug formed therein, Ru/TiN/Ti is formed as a lower electrode/barrier layer structure, and then, PZT is deposited thereon in a CVD process at a temperature of 430 degrees Celsius. FIG. 8B is a diagrammatic view showing the feature of the photograph of FIG. 8A.
It would be seen from FIGS. 8A and 8B that PZT/Ru is pealed off and lifted up from TiN only in the region of the W plug. This lifting is considered as follows: Since PZT causes a large stress, a stress lifting up the PZT film is generated and concentrated in a region above the W plug, because of a thermodynamic relation among the semiconductor substrate, the W plug, the barrier layer, the lower electrode and the PZT film.
If the lower electrode above the W plug was pealed off and lifted up from the barrier layer, the capacitor of the memory cell above the W plug becomes defective, with the result that the yield of the semiconductor memory drops. In addition, reliability of the device characteristics drops dependently upon the degree of lifting-up from the barrier layer (the degree of connection insufficiency).
Accordingly, it is an object of the present invention to provide a semiconductor memory which has overcome the above mentioned problem of the prior art, and a process for fabricating the same.
Another object of the present invention is to provide a semiconductor memory which has prevented the lifting of the lower electrode from the barrier layer in a region above the plug, thereby to improve the yield of production, and a process for fabricating the same.
The above and other objects of the present invention are achieved in accordance with the present invention in which a capacitor is formed of a lower electrode, a dielectric film and an upper electrode, and a barrier layer lying under the lower electrode is constituted to include at least a first metal film, a metal nitride film and a second metal film. The metal nitride film can be preferably formed of a nitride of a metal element of the first or second metal film.
Now, the principle of the present invention will be described. In order to overcome the above mentioned problems, the inventors made various experiments and studies, and found out that if a barrier layer under a lower electrode of a ferroelectric material capacitor (or a highly dielectric material capacitor) is formed to include a triplelayer structure in which a film of a nitride of a metal such as Ti and Ta is inserted between two metal layers, it is possible to effectively prevent the dielectric film (for example, PZT film) and the lower electrode (Ir or Ru) from being lifted up from the barrier film in a region above the plug.
A second metal layer constituting an uppermost layer of the triplelayer structure serves to elevate a tight adhesion to the lower electrode. The metal nitride film under the second metal layer is required not only for preventing diffusion of the material of the plug and oxygen, but also to prevent the lower electrode from being lifted up in a region above the W plug. This is confirmed on the basis of the result of experiments in which if PZT is deposited on Ru/Ti, the lifting occurs in a region above the plug. This phenomenon is considered that the upward diffusion of the plug material influences the lifting of the lower electrode.
Here, if the barrier layer is constituted of only the first metal and the metal nitride film laminated in the named order, it is not sufficient to prevent the lifting of the lower electrode in the region above the plug. This is confirmed on the basis of the result of experiments in which if PZT is deposited on Ru/Ti/TiN, the lifting occurs in a region above the plug.
Therefore, in order to prevent the pealing of the lower electrode, it is necessary to form the first metal layer under the metal nitride film, so as to form the triplelayer structure in which the first metal layer, the metal nitride film and the second metal layer are formed in the named order counted from a lower position. The metal nitride film is formed of a nitride of a metal element of the first or second metal film.
The reason for the first metal layer required to prevent the pealing of the lower electrode is considered that since crystallinity of the metal nitride film is influenced by crystallinity of the underlying film, the first metal layer can serve to relax a concentration of the stress above the plug.
Preferably, the triplelayer structure constituting the barrier layer is formed of a triplelayer film formed of a TiN layer sandwiched between Ti layers (Ti/TiN/Ti) or a triplelayer film formed of a TaN layer sandwiched between Ta layers (Ta/TaN/Ta). Ti and Ta have an excellent adhesion to Ir and Ru.
Here, Ti, TiN, Ta and TaN are materials frequently used in conventional LSI fabricating process, and therefore, a film of those materials can be formed by utilizing existing film formation machines. Therefore, it is possible to prevent elevation of the production cost of the semiconductor memory.
Further preferably, the upper electrode and the lower electrode of the ferroelectric material (or highly dielectric material) capacitor are formed of mainly Ru or RuOx, since within a platinum metal group, Ru is only one material which can be finely patterned by a chemical etching.
The frequency of occurrence of the lower electrode lifting is strongly dependent upon a film deposition temperature of the ferroelectric material (or highly dielectric material). According to experiments the inventors conducted, if the film deposition temperature of PZT exceeds 475 degrees Celsius, even if the barrier film is formed of the triplelayer film, the lower electrode lifting appears sometimes. Accordingly, the film deposition temperature of the ferroelectric material is preferably not greater than 500 degrees Celsius, and more preferably not greater than 475 degrees Celsius.
Thus, in the semiconductor memory in accordance with the present invention which includes an interlayer insulator film formed on a semiconductor substrate where a transistor or another active circuit element are formed, a plug reaching a surface of the interlayer insulator film, and a capacitor formed by forming a barrier layer, a lower electrode, a ferroelectric material film or a highly dielectric material film, and an upper electrode on the plug in the named order counted from a lower position, the lower electrode is formed of Ru, Ir or a conductive oxide, and the barrier layer is formed to a multilayer structure having at least three layers. In the multilayer structure, a layer in contact with the plug or the interlayer insulator film is formed of a first metal layer, and a layer in contact with the lower electrode is formed of a second metal layer, at least one layer of metal nitride film being formed between the first and second metal layers. The metal nitride film is formed of a nitride of a metal element of the first or second metal layer.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.